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Free engineering tool
Display Timing &
Configuration Generator
Turn display datasheet values into traceable timing, bandwidth, link-rate, and platform configuration references for RGB, LVDS, and MIPI-DSI interfaces.
- No installation
- Runs in your browser
- Free to use
Link budget within selected platform range
From datasheet to first configuration
Make display interface decisions with confidence
Validate the numbers that matter before schematic review, BSP integration, or panel bring-up.
Calculate accurately
Convert active pixels, porches, sync widths, refresh rate, and color depth into complete timing results.
Check link requirements
Estimate RGB bandwidth, LVDS serialization, or MIPI-DSI per-Lane data rate before selecting the host.
Start configuration faster
Generate adaptable references for RTOS, Linux, and Android platforms instead of transcribing every value manually.
One workspace, three interface families
Select the path your display uses
RGB / DPI
Calculate complete video timing and continuous parallel-bus data bandwidth.
- Pixel clock and total periods
- RGB565 / RGB666 / RGB888
- Bus width and frame-buffer size
LVDS
Check serialization requirements and document the mapping expected by the panel.
- Single Link / Dual Link
- VESA / JEIDA mapping
- Per-pair and total serial rate
MIPI-DSI
Estimate the D-PHY data-rate budget across Ports and Data Lanes.
- Single Port / Dual Port
- 1, 2, or 4 Data Lanes per Port
- Per-Lane rate and platform check
How it works
From panel parameters to usable results in three steps
- 1
Select an interface
Choose RGB, LVDS, or MIPI-DSI and start from a common resolution preset when appropriate.
- 2
Enter datasheet timing
Add H/V active pixels, porches, sync widths, refresh rate, pixel format, and link settings.
- 3
Review and configure
Check formulas and platform guidance, then copy or download the generated configuration reference.
Transparent calculations
See where every result comes from
The generator places values, units, and formulas together so you can compare them directly with the panel datasheet and host documentation.
HTotal × VTotal × FPSHActive × VActive × BPP ÷ 8Total DSI Rate ÷ Ports ÷ LanesIllustrative values using example timing. Your results update from the exact parameters you enter.
Platform configuration references
Start closer to your target system
Select a system and host to generate an adaptable starting point for your BSP.
Real-time systems
NXP i.MX RT · STM32 · Espressif ESP32
- MCUXpresso
- STM32Cube HAL
- ESP-IDF
Embedded Linux
Raspberry Pi · Rockchip RK35xx
- DRM panel timings
- Device Tree overlays
- VOP / DSI references
Android platforms
MediaTek · Qualcomm
- LCM parameters
- MDSS DSI panel DTSI
- Initialization templates
Platform limits are conservative early-design references. Always verify the exact processor, display controller, D-PHY, and BSP release.
Built for display integration
Useful from evaluation through bring-up
- HWHardware engineers checking clocks, buses, and link budgets
- SWEmbedded engineers preparing panel and BSP configurations
- PMProduct teams comparing displays, interfaces, and host options
- FAEApplication engineers supporting customer panel integration
Engineering notice
A strong starting point—not a production driver
The generated configuration does not replace the panel datasheet, processor reference manual, schematic, PCB review, or measured signal verification.
- Panel initialization commands and power sequencing remain panel-specific.
- RGB/BGR order, signal polarity, PCLK edge, and DSI operating mode must be confirmed.
- Dual-Port DSI split mode and LVDS mapping must match both endpoints.
Frequently asked questions
Common display timing questions
Practical answers for evaluating a panel before integration.
What information do I need from the panel datasheet?
Use the active resolution, target refresh rate, pixel format, HFP, HSYNC, HBP, VFP, VSYNC, and VBP values. For LVDS, also confirm VESA/JEIDA and Link count. For MIPI-DSI, confirm the Port count, Data Lanes per Port, and operating mode.
What is the difference between LVDS VESA and JEIDA?
They map the RGB bits onto LVDS channels differently. The setting must match the panel datasheet and physical wiring; a mismatch commonly causes incorrect colors.
Does MIPI-DSI support Dual Port?
Yes, when both the panel and host support two synchronized DSI Hosts. Dual Port is not simply an eight-Lane Host; the split mode and synchronization must be implemented by the complete system.
Why is pixel clock important for LVDS and MIPI-DSI?
Pixel clock defines the complete video cadence, including active video and timing intervals. LVDS serialization and MIPI-DSI video payload requirements are derived from that cadence.
Why is frame-buffer size shown in MiB instead of MB?
MiB is a binary memory unit: 1 MiB equals 1,048,576 Bytes. MB commonly uses the decimal definition of 1,000,000 Bytes.
Can I use the generated configuration directly?
Treat it as a configuration reference. Complete integration still requires panel-specific initialization, board routing, GPIOs, power sequencing, clock setup, BSP adaptation, and hardware verification.
Continue your display project
Explore displays and engineering support from VIEWE
Ready to check your display?
Bring your datasheet. Get the timing in minutes.
Use the free generator for initial evaluation, or contact VIEWE for display selection and integration support.