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1.Parallel Interface: LCD Interface
1-1 MCU Interface 8080/6800
Display raw data sent via Data bus according to control bus signal. Communication bandwidth depends on enabling speed running on Driver IC. QVGA 320×240 dot matrix LCD i.e., the communication bandwidth will be 320 * 240 / 8 bit (data width) * 60 fps = 576KHz at ENABLE signal.
Features:
- MCU interface include two types, 6800 and 8080. 8080 is the much more popular than 6800. Generally, MCU interface consist of 4/8/9/16bits data (like DB0, DB1, , , DB7; Note: 8bits is the most popular bits width), CS (chip select), RS (data register or instruction register select), RD (read enable), WR (write enable).
- PROs: Simple
- CONs: Need RAM, Speed is limited.
- Used in Mono character, graphic, small TFT (smaller than 4”)
1.2 Parallel RGB 16/18/24 bits
The RGB interface is to transmit the drive timing to the display driver IC through the data input/output in a parallel manner, including R/G/B data, vertical synchronization signal (V-SYNC, Vertical synchronizing signal), horizontal synchronization signal (H-SYNC), horizontal synchronizing signal), data enable (DE, Data Enable) signal, and clock signal PCLK (Pixel Clock). The display interface of RGB666 is as follows:
Display raw data transferred same as above. But the display resolution is getting higher and higher. i.e., WVGA 800 * 480 (pixels) * 60 fps = 23.04 MHz. (PCLK)
Features:
- RGB interface often been used in control large-scale high-resolution LCD display. It include 6/16/18bits data (like R0, R1, , , G0, G1, , ,B0, B1, , , ), VSYNC (Vertical synchronization), HSYNC (Horizontal synchronization).
- Advantage is that R,G,B data is written to LCD directly without GRAM, high speed. Normally used in large-scale high-resolution LCD.
- Disadvantage is to control LCD is more complex, and need more data wires than MCU interface.
- Application: Medium size TFT (3.5” to 8”)
- RGB interface includes 24 bit, 18 bit, 16 bit
2.Serial Interface
2.1 SPI (Serial Peripheral Interface)
SPI is a master-slave-based interface, usually with a Master (master device) and one or multi slave (slave devices). There are 4 pins on the interface. The connection method and hardware structure are as follows:
[SPI interface structure]
SCLK: The synchronous clock used by all devices. The master drives this clock and the slaves receive the clock.
MOSI: Master out, slave in. This is the main data line driven by the master to all slaves on the SPI bus. Only the selected slave clocks data from MOSI.
MISO: Master in, slave out. This is the main data line driven by the selected slave to the master. Only the selected slave may drive this circuit. In fact, it is the only circuit in the SPI bus arrangement that a slave is ever permitted to drive.
CS: Chip Select. This signal is unique to each slave. When active the selected slave must drive MISO.
[Example of SPI schematic]
Display data transferred in sequential. Display interface communication bandwidth i.e., QVGA 320 * 240 (pixels) * 16 bit (color depth) * 30 fps = 36.864 MHz.
2.2 IIC (Inter-Integrated Circuit) or alternatively known as I²C):
Different from the point-to-point (or point-to-multipoint) base of SPI, I²C is interfaced in the form of a data bus, which allows multiple master devices and multiple slave devices to be connected in series. The interface method and hardware structure are as follows:
[I²C schematic]
[Courtesy of Analog device]
Standard mode = 100K bit/s.
Full speed mode = 400K bit/s.
Fast mode = 1M bit/s.
High speed mode = 3.2M bit/s.
2.3 Serial RGB 6/8 bits
Display data transferred in RGB sequential. Display interface communication bandwidth i.e., QVGA 320 * 240 (pixels) * 3 dot * 30 fps = 6912000 Hz (DCLK).
2.4 LVDS: Low voltage differential signal.
It should name FPD-Link for the display interface.
LVDS is a technical standard introduced in 1994 that specifies electrical characteristics of a differential, serial signaling standard, but it is not a protocol. LVDS is a physical layer specification only; many data communication standards and applications use it and add a data link layer as defined in the OSI model on top of it. LVDS operates at low power and can run at very high speeds using inexpensive twisted-pair copper cables.
Early on, the notebook computer and LCD display vendors commonly used LVDS instead of FPD-Link when referring to their protocol. The term LVDS has mistakenly become synonymous with Flat Panel Display Link in the video-display engineering vocabulary.
Features:
- LVDS (Low-voltage differential signaling) is an electrical digital signaling standard that can run at very high speeds over inexpensive twisted-pair copper cables.
- Most used in big panels (>7”)
Example of LVDS Interface
2.5 MIPI CSI/DSI: Mobile Industry Processor Interface.
[Display view of DSI.]
MIPI Alliance aimed at reducing the cost of display controllers in mobile devices. It defines a serial bus and a communication protocol between the host, the source of the image data, and the destination device. It is the expected target at LCD and similar display technologies.
[System view of DSI.]
DSI specifies a high-speed (e.g., 4.5 Gbit/s/lane for D-PHY 2.0) differential signaling point-to-point serial bus. This bus includes one high-speed clock lane and one or more data lanes.
Image data on the bus is interleaved with horizontal and vertical blanking intervals signals. The data is transferred to the display in real-time and not stored by the device to save frame buffer memory in the display. However, it also means that the device must be continuously refreshed (at a rate such as 30 or 60 frames per second) or lose the image. Image data is only sent in HS mode. When in HS mode, commands are transmitted during the vertical blanking interval.
Features:
- MIPI (Mobile Industry Processor Interface) Alliance, DSI (Display Serial Interface)
- Aimed at reducing the cost of display controllers in a mobile device. It is commonly targeted at LCD and similar display technologies. It defines a serial bus and a communication protocol between the host (source of the image data) and the device (destination of the image data)
- MIPI Interface is getting more and more popular.
An Example of MIPI Interface
2.6 eDP interface
DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). The interface is primarily used to connect a video source to a display device such as a computer monitor, and it can also carry audio, USB, and other forms of data.
DisplayPort was designed to replace VGA, DVI, and FPD-Link. The interface is backward compatible with other interfaces, such as HDMI and DVI, through the use of either active or passive adapters. It is mostly used for larger size and higher resolution displays.
eDP Interface
3. Comparison on LCD display interface
Which interface is the best? There is no absolute answer to this question. The users should choose the suitable interface for their applications, not the best. Let’s see the following comparison of the pros and cons of these interfaces.
| Display Interface | Resolution | Speed | Pin Count. | Noise | Power | Connect Distance | Cost |
| MCU 8080/6800 | Middle | Low | More | Middle | Low | Short | Low |
| RGB 16/18/24B | Middle | Fast | More | Worst | High | Short | Low |
| SPI | Small | Low | Less | Middle | Low | Short | Low |
| I²C | Small | Low | Less | Middle | Low | Short | Low |
| Serial RGB 6/8B | Middle | Fast | Less | Worst | High | Short | Low |
| LVDS | Large | Fast | Less | Best | Low | Long | High |
| MIPI | Large | Fastest | Less | Best | Low | Short | Average |
| eDP | Large | Fastest | Less | Best | Low | Long | High |
